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1 www.semtech.com microbuddy ? support ic for microcontrollers power management SH3003 may 23, 2006 three components make a complete system: any microcontroller, the SH3003, and a bypass capacitor. this low-cost system would consume very little power and have clock-frequency accuracy of 0.5%. a fourth component, a 32.768khz crystal, raises the clock frequency accuracy to 0.0256% ( 256 ppm). the SH3003 can operate completely stand-alone, or un- der control of the microcontroller. a single-wire interface handles both bi-directional communications and the in- terrupt/wake-up signal from the SH3003. the SH3003 stores all con guration, calibration, parameters, and sta- tus information in a 36-byte bank of control registers. on reset, most of these are reloaded with defaults from the factory-set non-volatile memory. the microcontroller can change any settings on the y. if some of the settings must remain xed, a comprehensive set of write-protect bits is provided for several related groups of registers (with both permanent write-inhibit and lock/unlock capabilities). a backup power source may also be connected to the SH3003. the ic can directly accommodate 2/3-cell zinc- carbon/alkaline, 2/3-cell mercury, 2/3/4-cell nicd/nimh, one cell li/li+ batteries, or a super cap. the programmable SH3003 microbuddy? ( buddy?) provides all mandatory microcontroller support functions: cpu supervisor clock management system real-time support auxiliary functions ? ? ? ? home automation and security consumer products portable/handheld computers industrial equipment any microcontroller-based product ? ? ? ? ? highly integrated ic - 3mm x 3mm x 0.9mm, 16-lead mlp (qfn) package cpu supervisor low vdd reset programmable from 2.3v to 4.3v watchdog timer with programmable time out periods both active-high and active-low reset outputs clock management system replaces high-frequency (hf) crystal or resonator programmable clock output from 32.768khz to 16mhz speed shift between multiple clock frequencies adjustable spectrum spreading for emi reduction directly supports microcontroller stop function deep sleep with instantaneous auto-wakeup real-time support 179 year real-time clock, battery-backup capable dedicated 32.768khz buffered clock output built-in trim for 32.768khz oscillator to 4ppm programmable periodic interrupt/wakeup timer auxiliary functions 4-byte (32-bit) scratchpad ram, loaded on reset with factory-set value (zero or optional id code) all settings programmable in real time, defaults restored from nonvolatile memory on reset operates from 2.3v to 5.5v idd < 850 a /2mhz, < 3ma / 16mhz, <10 a/ standby - i bup < 2 a / i bsb <50na (battery back up/standby) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description features applications
2 ? 2006 semtech corp. SH3003 www.semtech.com not authorized for release outside of semtech - draft power management typical application circuit SH3003 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 vdd x in x out gpio with int n reset gnd v+ c bypass b tm controller typical application circuit with high clock accuracy
? 2006 semtech corp. www.semtech.com power management 3 SH3003 power management parameter symbol min max units supply voltages on v dd or v bak relative to ground v dd -0.5 5.5 v input voltage on clk in , i o /i nt , test v in 1 -0.5 vdd + 0.5 v input voltage on clk sel v in 2 -0.5 vreg + 0.5 v input current on any pin except v reg i in 110ma input current on v reg i in 2 150 ma ambient operating temperature t op -40 85 oc storage temperature t stg -55 60 oc ir re ow temperature - SH3003imltr t irrt 240 oc ir re ow temperature - SH3003imltrt t irrt 260 oc parameter symbol min typ max units notes case temperature t op ?40 +85 oc supply voltage v dd 2.3 5.5 v supply current, clk out = 16 mhz (1) i dd 3ma supply current, clk out = 8 mhz (1) i dd 1.8 ma supply current, clk out = 2 mhz (1) i dd 0.9 ma standby current, 32.768khz crystal (2) i sb 8 a clk32 disabled standby current, 32.768khz rc oscillator (2) i sb 10 a clk32 disabled backup supply voltage (2) v bak 2.3 5.5 v backup current, 32.768khz crystal (2) i bup 2 a clk32 disabled backup current, 32.768khz rc oscillator (2) i bup 8 a clk32 disabled backup standby current (2) i bsb 50 na vdd > vbo notes: 1) assuming load on clk out < 20pf 2) assuming temperature < 60oc electrical characteristics absolute maximum ratings exceeding the speci cations below may result in permanent damage to the device or device malfunction. operation outside of the parameters speci ed in the electrical characteristics section is not recommended.
4 ? 2006 semtech corp. SH3003 www.semtech.com not authorized for release outside of semtech - draft power management parameter symbol min typ max units crystal operating frequency f op 32.768 khz clk32 duty cycle dc 25 75 % start-up time t st 3 secs xin/xout padding capacitance after power-up c pup 12.5 pf minimum x in /x out padding capacitance c min 10 pf maximum x in /x out padding capacitance c max 40 pf padding capacitance resolution c res 2pf x in switching threshold v th 0.6 v x in to clk32 delay t d 0.5 ppm/c clk32 frequency stability (crystal-dependent) f s 1 s clk32 cycle-to-cycle jitter j 0.05 % clk32 rise/fall time (10pf load) t rf 10 ns clk32 logic output low (0.5ma load) v ol 0.25 0.5 v clk32 logic output high (0.5ma load) v oh -0.5 -0.25 ref vdd* crystal oscillator *note: v dd here is v dd during normal operation and v bak during battery backup. parameter symbol min typ max units external 1m referenced nominal frequency f ext 32.768 khz internal 1m referenced nominal frequency f int 32.768 khz clk32 duty cycle* dc 40 60 % programmed frequency accuracy at 25c f st -1 +1 % absolute accuracy (temp. & supply external 1m )f de 2 % absolute accuracy (temp. & supply internal 1m ) f di 3 % frequency temperature stability (ext. 1m )f se 100 ppm/c frequency temperature stability (int. 1m )f si 200 ppm/c power on start-up time t st 70 s clk32 cycle-to-cycle jitter* j 0.1 % 32.768khz rc oscillator *note: after power-up, pin clk32 is disabled, pin r ref is also disabled, and the oscillator is set to operate without the external reference resistor. electrical characteristics (continued)
? 2006 semtech corp. www.semtech.com power management 5 SH3003 power management parameter symbol min typ max units v dd switching threshold after power-up v bo(pup) 2.3 v v dd switching threshold for min code v bo(min) v bo(min) 2.27 2.3 2.33 v v dd switching threshold for max code v bo(max) 4.2 4.3 4.4 v v dd threshold resolution v res 33 mv v dd hysteresis v hys 50 mv falling v dd threshold switch delay td 2.5 s threshold d ac settling time tdac 4 ms minimum v dd for valid nrst and r st v dd(min) 1v parameter symbol min typ max units minimum operating freq. (start-up default = 16mhz) f min 5.6 8 mhz maximum operating frequency f max 16.8 21 mhz frequency resolution f res -0.3 2 khz programmed frequency accuracy at 25c f st +0.3 % frequency drift over temperature and supply f drift 0.5 % clkout cycle-to-cycle jitter (spread spectrum off) j 0.1 % start-up time from standby t start 2 s settling time to 0.1% after hf digitally-controlled oscillator (dco) code change t sett 10 s clk out duty cycle dc 40 60 % frequency temperature stability f ts 100 ppm/c short-term frequency stability f s 0.5 %/sec minimum spread spectrum range* ss( min ) 32 khz maximum spread spectrum range* ss( max ) 256 khz clkout rise/fall time (20pf load) t rf 3ns clkout logic output low (4ma load) v ol 0.25 0.4 v clkout logic output high (4ma load) v oh -0.4 -0.25 ref vdd high-frequency oscillator (hfo) * note: after power-up, spectrum spreading of the high-frequency oscillator is disabled. programmable reset electrical characteristics (continued)
6 ? 2006 semtech corp. SH3003 www.semtech.com not authorized for release outside of semtech - draft power management pin pin name type pin function t thermal pad - connect to ground 1v ss power ground, 0v - all v ss pins and test (v ss ) pin must be connected together. 2 v reg power output of internal voltage regulator, 2.2v nominal. this pin can power exter- nal loads of < 5ma. if load is ?noisy? it requires a bypass capacitor. may be left unconnected or used as a high logic level signal for clk sel pin. 3v dd power main power supply, +2.3 to +5.5v 4v bak power back-up power supply for real-time clock, +2.3 to +5.5v (+1.8 to +5.5v typical). this voltage can be higher or lower than v dd . connect a backup battery or backup capacitor (with external recharge circuit). connect to v dd if not used. 5x in analog in oscillator pins for optional external low frequency crystal, typically 32.768khz crystal with nominal 12.5pf load cap. keep open or connect to v ss if not used. 6x out analog out 7 clk sel digital in a logic low level selects the internal 32.768khz rc oscillator (clk sel tied to v ss ). a high state on this pin selects the 32.768khz crystal oscillator (clk sel is connected to v reg ). the SH3003 always starts up using the internal 32.768khz rc oscillator. if clk sel is high, the internal 32.768khz clock switches to the crystal oscillator once it has stabilized, and rc oscillator is disabled for power conservation. do not connect clk sel to any signals except v ss or v reg . clk sel must not be left open. 8v ss power ground, 0v. all v ss pins and test (v ss ) pin must be connected together. device package SH3003imltr mlp 3x3mm, 16 pins SH3003imltrt mlp 3x3mm, 16 pins, lead-free evk-sh3000usb sh3000 evaluation kit sh3000ek.pdf sh3000 evaluation kit user guide sh3000um.pdf sh3000 reference manual top view 1 2 3 4 12 11 10 9 16 15 14 13 5678 mlp 16: 3x3 16 lead t vss io/int clk in clk out test vss rst nrst nrst vss clksel xout xin vbak vdd vreg clk 32 pin con guration ordering information pin descriptions
? 2006 semtech corp. www.semtech.com power management 7 SH3003 power management pin descriptions (continued) pin pin name type pin function 9r ref analog optional 1m external bias resistor for internal 32.768 khz rc oscillator. can be used to set, trim or modulate the internal rc oscillator. keep open if not used. 10 n rst digital out active low system reset output. asserted with a strong low state when a reset condition occurs. weakly pulled to v dd internally when not active. this signal is valid for v dd as low as 1v. keep open if not used. 11 r st digital out active high system reset output. asserted with a strong high state when a reset condition occurs. weakly pulled to v ss internally when not active. this signal is valid for v dd as low as 1 v. keep open if not used. 12 test (v ss ) digital in factory test enable. all v ss pins & test (v ss ) pin must be connected together. 13 clk32 digital out buffered internal 32.768 khz clock, derived according to the clk sel pin setting. pin uses backup power for the buffer when v dd is not present. when driving high, this signal is either at v bak or v dd (if v dd is higher than the reset threshold). when enabled, this signal runs continuously independent of clk out activity. minimize the external load to reduce power consumption during backup opera- tions. when disabled, this pin is driven to v ss . keep open if not used. 14 i o /i nt i/o serial communications interface and interrupt output pin. pin is internally weakly pulled to opposite of programmed interrupt polarity. if interrupt is programmed to be active low, pin is weakly pulled to v dd when inactive. keep open if not used. 15 clk in digital in clock activity sense input. detects when target microcontroller enters stop mode (which disables its clock). connect to the microcontroller?s clock output or oscil- lator output pin. connect to v ss when not used. clk in must not be left open. 16 clk out digital out programmable high frequency clock output. connect to the target microcon- troller?s clock input or oscillator input pin. keep open if not used. t thermal pad pad for heatsinking purposes. connect to ground plane using multiple vias. not connected internally.
8 ? 2006 semtech corp. SH3003 www.semtech.com not authorized for release outside of semtech - draft power management block diagram clk32 microcontroller v+ v dd 32.768 k h z x in x out r eset i/o pin clk sel v bak v reg lf oscillator select logic reset drivers & logic v dd monitor watchdog hf oscillator & fll real time clock periodic interrupt / wake-up timer x tal oscillator rc oscillator regulators & battery back-up nonvolatile memory calibration & default settings serial i/o control logic 8 clock driver & start/stop logic post-scaler 2 3 4 9 10 11 12 5 6 7 13 14 15 16 interrupt v dd v ss x in x out voltage reference clk out clk in r ref rst n rst t est io/i nt SH3003 buddy? 1 v ss
? 2006 semtech corp. www.semtech.com power management 9 SH3003 power management application information the SH3003 is a single-chip support system for microcontrollers, microprocessors, dsps and asics. it consists of four major functional blocks, each block having numerous enhancements over alternative solutions. the major modules are the cpu supervisor, the clock management system, the real-time support, and the auxiliary functions. the entire chip is controlled by the set of internal registers and accessed via the single-pin serial interface. all of the settings, con guration, and calibration or operating parameters are programmable and re-programmable at any time. all of the parameters required for stand- alone operations are initialized on reset from the built- in factory-programmed nonvolatile memory. this allows the SH3003 to operate autonomously for most of its supervisory functions. the stand-alone operations do not require the use of the serial interface or any of the initialization and control operation, but without these, the full potential bene t of the SH3003 may not be realized. in the preferred con guration, where the SH3003 is tightly coupled to the target micro, the SH3003 offers an unprecedented level of design exibility in clock and power usage management. the SH3003 is a particularly desirable integration because the built-in features interact and meld to produce more useful system level functions. for example, on power-up, the SH3003 can quickly release the reset lines on its cpu supervisor module because the clock signal from the clock management system is guaranteed to be running and stabilized. an ordinary reset circuit must hold reset active for a long time to allow an unknown crystal to start up and stabilize. the SH3003 offers several ways to minimize system power consumption, such as allowing the target processor to enter deep sleep by stopping its clock completely, and to wake up as often as necessary with no external support. the clock can be programmed to start up at a given frequency, and software can adjust it dynamically to manage power consumption and different operating modes. users should consider the interactions of the major functional blocks to gain the maximum advantage from the SH3003. the individual functional blocks are described in the following sections. default start-up parameters while the operating parameters of the SH3003 are programmable by the host microcontroller at any time, the default start-up parameters and appropriate calibration values are programmed into the chip?s non- volatile memory at the factory. this enables the SH3003 to be used stand-alone or in an embedded application with minimal microprocessor intervention. default start-up parameters for the SH3003 are: reset and v bo voltage level is 2.3v clk out frequency is 16.0mhz clk32 output is disabled spread spectrum is disabled internal rc oscillator is calibrated (to nominal frequency of 32768hz internal load capacitors on the 32.768khz crystal oscillator pins are set to 12.5pf. ? ? ? ? ?
10 ? 2006 semtech corp. SH3003 www.semtech.com not authorized for release outside of semtech - draft power management parameter min typ max units vbo for min code (000000) 2.27 2.3 2.33 v vbo for max code (111111) 4.2 4.3 4.4 v step resolution 33 mv application information (continued) cpu supervisor the SH3003 has two supervisory functions that man- age the reset of the target processor, a low v dd monitor (brownout detector) and a watchdog timer, see figure 1. both functions are integrated with the clock management system to provide a more complete system solution than stand-alone components. the SH3003 has both active high and active low reset output pins. both are driven strong to the active state and weak to the inactive state. this eliminates the need for ex- ternal pull-ups and allows various reset sources to be con- nected together in a wire-or con guration. (this makes it simple to set up a manual reset circuit.) a set of ags in the register map indicates the source of the reset to the system software. table 1 low v dd reset the SH3003 drives the reset pins active whenever v dd is below the value of v bo , the brownout reset threshold, pro- grammable from 2.3v to 4.3v in average steps of 33mv, see table 1. the default v bo value is loaded on power-up from the fac- tory-programmed non-volatile memory. it can be re-pro- grammed at any time or it can be permanently protected from any changes by setting the v bo lock ag or a write- protect ag. figure 1. cpu supervisor --- low v dd / brownout detector, watchdog, reset logic & drivers noise filter 3 v dd v high v low threshold d/a 4.40 v 2.30 v hysteresis 50mv typ . reset logic & minimum duration timer pwr ok temperature- compensated voltage reference 10 n rst 11 rst v dd 20 k 20 k u nderflow 1 0 32khz
? 2006 semtech corp. www.semtech.com power management 11 SH3003 power management on power up both the active-high and active-low reset sig- nals are driven active. these outputs are typically valid for a v dd level of at least 0.5v, and guaranteed to be valid for a v dd level of 1.0v. the reset outputs remain active until v dd rises and stays above the level of (v bo + v hyst ), where v hyst is a small xed amount of hysteresis, nominally 50mv, added to pre- vent nuisance reset activations (when v dd slowly changes near the level of v bo and some noise or power glitching is present). at the level of (v bo + v hyst ) the power supply is consid- ered valid. in case of the initial power-up, the reset is then driven inactive once 6ms of valid power have elapsed. in the case of brownout, the reset is released after a de- lay of 6ms (but no less than 12ms from the beginning of the brownout). such a fast reset is possible because the SH3003 provides a fast-starting clock that is free of crys- tal start-up time requirements. this gives the SH3003 an advantage over most external reset circuits, which must have a long reset pulse duration to accommodate long and unpredictable crystal start-up times. the SH3003 guarantees that a valid and stable clock is available 2ms before the reset signals are negated, so that internal synchronous reset and initialization of the target micro can proceed normally. application information (continued) low v dd reset (continued) since the clock is only active for the last 1 or 2ms of the reset interval, when v dd has already been valid for some time, energy savings are realized and the start-up of the whole system is made easier. the commonly used reset approach forces the processor to turn the oscillator on and to run at full speed (thus consuming full power) dur- ing the critical time when the (possibly depleted) battery is trying to raise v dd to an acceptable level. in contrast, the SH3003 allows the power source to charge the bypass capacitors and raise the level of v dd with little additional load. only when power has stabilized is the target micro permitted to start expending energy. when a brownout event occurs, the SH3003 continues to provide the clock to the target processor, but at a reduced frequency between 500khz and 1.0mhz. after a delay of 2ms this clock is stopped, automatically lowering the en- ergy consumption of the whole system, (see figure 2). a noise filter (see figure 1, page 10) prevents reset ac- tivations from noise and small power glitches on the v dd line. a typical behavior is shown in figure 3 for the v dd level just above v bo and various amplitudes and durations of the negative-going spikes. when vdd is falling, both reset lines are guaranteed to activate within 5 s from the time v bo is crossed over. v dd rst n rst clk out figure 2. operations of low v dd / brownout detector 1v v bo v bo +v hyst 3-5 ms 12 ms minimum 2 ms 2 ms 1 ms undefined normal f out reduced f out 0.5-1.0 mhz 6 ms 0 5 10 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 am plitude, v duration, s guaranteed no reset guaranteed reset duration amplitude figure 3. response to negative voltage spikes
12 ? 2006 semtech corp. SH3003 www.semtech.com not authorized for release outside of semtech - draft power management the second circuit for supervising the processor is the watchdog timer. whereas the low v dd /brownout detector monitors supply voltage, the watchdog timer monitors be- havior. it is based on a programmable timer that must be restarted periodically by the host micro. if software fails to restart the timer, the watchdog resets the processor. restarting the timer takes considerable processing, mak- ing it unlikely that it would occur accidentally, as might happen for a simple pin-strobe con guration of typical watchdog ic. the watchdog is disabled after reset occurs. it stays dis- abled until initialized by the host processor. the initializa- tion requires the watchdog clock mode to be selected (see figure 1) and the 7-bit time-out value to be set. as soon as the time-out is written, the watchdog begins operations and can not be stopped; also, the time-out value and or clock source can no longer be changed. the two clock sources available for the watchdog are the internal 32.768khz clock and the clk out signal. when operating from the 32.768khz source, the time-out inter- val is programmable from 7.8125ms to one second with resolution of 7.8125ms. the internal 32.768khz clock is running all the time, therefore the time-out duration is xed and predictable. when operating from the clk out signal the time-interval is programmable between 256 and 32768 cycles of clk out with resolution of 256 cycles. the actual time-out duration is variable and depends both on the frequency of clk out signal and the amount of time target micro spends in the stop mode, when the clk out signal is also stopped. these two clock modes, together with the programmable time-out value, allow the SH3003 exceptional exibility, previously unattainable by existing discrete watchdog so- lutions. the watchdog timer is kept from timing out by periodic reload of the time-out value, triggered by a write of a code byte to the watchdog reload register. as a further safety measure, there are two different and alternating code bytes that should be written to the same watchdog re- load register. the code values are 0x5a and 0xc3. the timer is reloaded after every write of a single code byte. the code byte should be written to the watchdog reload register, or reset is activated when the watchdog timer expires. also, reset is initiated immediately if the value of the code byte is incorrect or out of sequence. when the watchdog triggers the reset, its duration is 12ms. using two separate software routines, each to write one of the code values, results in the highest level of system se- curity. these routines must execute in the correct order. it is unlikely that runaway code could manage this. in addi- tion, this design makes it dif cult for the code to become stuck in a tight loop resetting the watchdog. application information (continued) watchdog timer
? 2006 semtech corp. www.semtech.com power management 13 SH3003 power management application information (continued) clock management system the SH3003 provides a exible tool for creating and man- aging clocks, a versatile and accurate ?any frequency? clock synthesizer (see figure 4). it is capable of generat- ing any frequency in the range of 62.5khz to 16.0mhz, with worst-case resolution of 0.0256% (256ppm). the in- ternal 32.768khz clock can also be routed to the clk out pin (and hf oscillator stopped for energy savings). the objectives, features, and behavior of the clock man- agement system are aimed towards the systems that utilize a microcontroller, a microprocessor, a dsp or an asic. the SH3003 permits the automatic sensing of the inten- tions of the host processor, an industry rst. the SH3003 shuts down its clock output when it senses that the host processor issued a stop instruction. subsequently, the SH3003 idles, consuming less than 10 a. as soon as the host exits the stop mode, the SH3003 instantaneously starts to supply a stable clock (< 2 s wake-up). a typical system, constructed with a ce- ramic resonator or a crystal as the frequency determining element, must wait at least several hundred microsec- onds (for a resonator), or as much as 100ms or more (for a hf crystal), to re-start the oscillator. the SH3003 allows the response to and service of an event to nish with a speed previously unattainable for a simple microproces- sor. a system with a traditional clock approach may be as much as 100x ? 10,000x slower. clock generator operation the frequency synthesizer in the SH3003 is constructed from the 2:1 tunable 8.0 ?16.0 mhz hf oscillator followed by a programmable ?power-of-two? post-divider (see fig- ure 4). the clock source selector and the programmable post- scale divider allow instantaneous switching between the 32.768khz internal clock and divided-down hf oscillator output. there is no settling or instability when the switch occurs. this is a preferred method for clock control in computing systems, when the large ratio between high and low frequency of operations allows for correspond- ingly large and instantaneous savings in power consump- tion. post-scaler (divide by 1, 2, 4, 8, 16, 32, 64, 128) figure 4. simplified hf oscillator system 32.768 khz s tart /s top 16 15 clk out clk in clock buffer and glue logic hf digitally controlled oscillator 8-16 mhz 18-bit dco code register clock on force dco on clock source 1 0 spectrum spreading controls frequency locked loop logic 13-bit frequency set value
14 ? 2006 semtech corp. SH3003 www.semtech.com not authorized for release outside of semtech - draft power management application information (continued) when the hf oscillator is operating alone, it can set the frequency of the clock on the clkout pin to 0.025%, and maintain it to 0.5% over temperature. this com- pares favorable with the typical 0.5% initial clock accu- racy and 0.6% overall temperature stability of ceramic resonators. the SH3003 replaces the typical resonator, using less space and providing better performance and functionality. the hf oscillator can also be locked to the internal 32.768khz signal. the absolute accuracy and stability of the hf clock depends on the quality of the 32.768 khz internally generated clock; the low-frequency (lf) oscilla- tor system is described later in this document. when the real-time clock module of the SH3003 is used for high- accuracy timekeeping, an external 32.768 khz crystal used as a reference for rtc provides excellent accuracy and stability for the clock management system. the SH3003 employs a frequency locked loop (fll) to synchronize the hf clock to the 32.768khz reference. this architecture has several advantages over the com- mon pll (phase locked loop) systems, including the ability to stop and re-start without frequency transients or instability, and with instant settling to a correct frequency. the conventional pll approach invariably includes a low- pass filter that requires a long settling time on re-start. the primary purpose of the fll is the maintenance of the correct frequency while the ambient temperature is changing. as the temperature drift of the hf oscillator is quite small, any corrective action from the fll system is also small and gradual, commensurate with the tempera- ture variation. clock generator operation (continued) the fll system in the SH3003 is unconditionally stable. to set a new frequency for the fll, the host processor writes the 13-bit frequency set value. the resulting out- put frequency is calculated using simple formulas: [1] and [2] (reference frequency is 32.768khz): fosc = 2048 hz * (frequency set value + 1) [1] fout = fosc / (post-divider setting) [2] for example, a post-divider setting of 8 and the fre- quency set value of 4000 (0x0fa0) produce an output frequency of 1.024mhz. programmable spectrum spreading most commercial electronic systems must pass regulato- ry tests in order to determine the degree of their electro- magnetic interference (emi) affecting other electronic de- vices. in some cases compliance with the emi standards is costly and complicated. the SH3003 offers a technique for reducing the emi. it can be a part of the initial design strategy, or it can be applied in the prototype stage to x problems identi ed during compliance testing. this feature of the SH3003 may greatly reduce the requirements for radiofrequency shielding, and permits the use of simple plastic casings in place of expensive rfi-coated or metal casings. the SH3003 employs programmable spectrum spreading in order to reduce the rf emissions from the processor?s clock. there are ve possible settings; please see table 2 for operating and performance gures in the 8-16mhz range.
? 2006 semtech corp. www.semtech.com power management 15 SH3003 power management application information (continued) programmable spectrum spreading (continued) setting spreading bandwidth khz peak emi reduction (guaranteed db) peak emi reduction (measured db) en cfg1 cfg0 0x x off 0 0 10 0 32 -3 -3 10 1 64 -6 -7 1 1 0 128 -9 -10 1 1 1 256 -12 -15 table 2 - emi reduction with spectrum spreading spectrum spreading is created by varying the frequency of the hf oscillator with a pseudo-random sequence (with a zero-average dc component). the maximum-length sequence (mls) 8-bit random number generator, clocked by 32.768khz, is used. only four, ve, six, or seven bits of the generated 8-bit random number are used, according to the con guration setting. maximum uctuations of the frequency depend on the selected frequency range and the position within the range. selecting the hf oscillator frequency to be near the high end of the range limits the peak variations to 0.1%, 0.2%, 0.4%, or 0.8% (corresponding to the con guration setting).
16 ? 2006 semtech corp. SH3003 www.semtech.com not authorized for release outside of semtech - draft power management application information (continued) the SH3003 has two support modules that are speci - cally designed for various real time support functions. they are the real-time clock and the periodic interrupt / wakeup timer. both of these units as well as other func- tions of the SH3003 depend on the internal 32.768khz clock for accuracy. the SH3003 allows a trade-off between the cost of a sys- tem and its accuracy. for some devices, a single SH3003 without any support components provides suf cient ac- curacy. these units can operate with processor clock accuracy of 0.5% and the accuracy of the real-time system of 3%. at the other end of the spectrum, with one external com- ponent (a 32.768khz crystal), the SH3003 can provide a processor clock accuracy of 256ppm (0.0256%) and the accuracy of the real-time system of 4ppm ( 0.0004%). real time support special operating modes the SH3003 can operate stand-alone, without connec- tions to the in and out terminals of the host?s oscillator. for example, a bank of SH3003 chips can generate sev- eral different frequencies for simultaneous use in the sys- tem, all controlled by a single micro (and possibly sharing one 32.768khz crystal by chaining the clk32 pin to xin pin on the next device). in this case the clk in pin should be connected to v ss . the clock output on the clk out pin is continuous; the correct operating mode is automatically recognized by the SH3003. a microcontroller may not have a stop command. with the SH3003, this controller can do a ?simulated? stop by issuing an instruction to the SH3003 to stop the clock. this command is accepted only if the periodic interrupt / wakeup timer has started (otherwise, once the system is put to sleep, it would never wake up again). this mode of operations is only possible if the host processor is ca- pable of correct operations with clock frequency down to zero, and keeps all of the internal ram alive while the clock is stopped.
? 2006 semtech corp. www.semtech.com power management 17 SH3003 power management this module provides the 32.768khz clock to all internal circuits and to the dedicated output pin, clk32. if en- abled, the clk32 output continues normal operations when vdd is absent and backup power is available. when the power is rst applied to the SH3003, the rc oscillator takes over. it supplies the 32.768 khz clock for start-up and initialization. however, if the clksel pin is set high, then the crystal oscillator is enabled. once the crystal has started and stabilized, the internal 32.768 hz clock switches to the very accurate crystal frequency; see figure 5. just like the vbo value for the reset circuit, the default calibration values for the rc oscillator are loaded on pow- er-up from the factory-programmed non-volatile memo- ry. they can be re-programmed at any time or they can be permanently protected from any changes by setting the lock ag or a write-protect ag. factory calibration brings the frequency of the rc oscillator within % of the 32.768khz for the internal reference resistor, and 2% for the external 1m 1% resistor, over the entire temperature and supply voltage range. the frequency of the rc oscillator can be tuned or mod- ulated by varying the external reference resistor, which should be located as close as possible to rref, pin 9. application information (continued) 5 6 9 7 v reg rc oscillator x- tal rc 13 internal 32.768 khz clock x-tal stable? external reference resistor 1 m 1% or variable internal r ref 32.768 khz crystal 12.5 pf load capacitance figure 5. simplified lf oscillator system 1 clk32 x in x out clk sel r ref 8 v ss v ss clk32 o n 4-bit value 6-bit value 4-bit value lock / unlock logic lock logic i nternal r ref o n from / to serial i/o the crystal oscillator has the useful feature of adjustable load capacitors. it permits tuning of the circuit for initial tolerance of the crystal (often 20ppm) as well as an ad- justment for the required load capacitance (with possible variations from the pcb layout). while the oscillator was designed for a crystal with a nominal load capacitance of 12.5pf, the circuit accommodates any value from ~7pf to 22pf (depending on parasitics of the layout). all of these corrections can be performed when the part is already installed on the pcb, in the actual circuit. the default value for load capacitance (12.5pf) loaded on power-up from the factory-programmed nonvolatile mem- ory can be re-programmed at any time (following a secure process of unlocking the load capacitance value register and immediately writing a new setting), or it can be com- pletely protected from any changes by a permanent write- protect ag. this adjustment can set the frequency of the crystal oscillator to within 4ppm of the ideal value. as a reference, a typical 32.768khz crystal changes its fre- quency 4ppm for a 10c change in temperature. since the temperature characteristics of crystals are well known and stable, the host processor is free to implement an algorithm for temperature compensation of the crystal oscillator using the adjustable load capacitors, with re- sulting accuracy of 4ppm over the entire temperature range. low frequency (lf) oscillator system
18 ? 2006 semtech corp. SH3003 www.semtech.com not authorized for release outside of semtech - draft power management application information (continued) using the 4ppm, 32.768khz clock from the lf oscillator, the real-time clock module keeps time with a maximum error as low as two minutes per year. this compares favorably with a conventional error of two minutes per month for the typical rtc chip. the hardware of the real-time clock is capable of 179-years of calendar operations (see figure 6). all counting-chain values are loaded at the same time into corresponding registers when the fractions register is read. all values from registers are loaded into the counting-chain when the fractions register is written. the rtc continues normal opera- tions when v dd is absent, if backup power is available. real-time clock 14 figure 6. real time clock and periodic interrupt / wakeup timer io/i nt 16-bit counter days (bin) 0 - 65535 256 hz 32-bit time interval 32-bit counter 32-bit comparator 32-bit latch interrupt logic serial i/o r eset 1 hz lsb msb minutes (bcd) 0 - 59 seconds (bcd) 0 - 59 fractions (bin) 0 - 255 hours (bcd) 0 - 23 32-bit latch l oad l oad lsb current timer value lsb msb 32.768 khz
? 2006 semtech corp. www.semtech.com power management 19 SH3003 power management simple and versatile, the periodic interrupt/wakeup timer can be used to create very accurate recurring interrupts for use by the host micro. with some minimal software support from the host processor, it can also be used to create alarms, with practically unlimited duration. while the timer is running, the host processor may be halted, consuming no energy. the interrupt wakes up the processor, which can perform the requisite task and go back to sleep, until the next periodic interrupt. this mode of operation can achieve extremely low average power consumption. a 32-bit counter clocked by 32.768khz, producing a minimum interval of 30.5 s and the maxi- mum interval of 36.4 hours, creates the timer. after reset, the timer is stopped until the new value for the time interval is written into the 4-byte time interval register. when the least signi cant byte (lsb) is written, the whole value is moved to the time interval latch, the counter is reset and starts to increment with the 32.768 khz clock. when the 32-bit comparator detects a match, an interrupt is generated and the counter is reset and starts the next timing cycle. although the counter cannot be written to, the current val- ue from the counter can be read at any time. the whole 32-bit value is loaded into the 32-bit current timer value latch when the least signi cant byte is read. this pre- vents errors stemming from the nite time between the readings of individual bytes of the current value. periodic interrupt/wakeup timer application information (continued) auxillary functions scratchpad ram four bytes of general-purpose ram reside on the SH3003. voltage regulator pin v reg can be used as a nominal 2.20v reference volt- age or a supply source for small loads (< 2ma). a bypass capacitor may be necessary between this pin and v ss if the load generates large current transients or a low ripple reference is required.
20 ? 2006 semtech corp. SH3003 www.semtech.com not authorized for release outside of semtech - draft power management application information (continued) a single line is used to convey bi-directional information between the SH3003 and the processor, and as the inter- rupt line to the processor. the polarity of the interrupt signal is programmable. the SH3003 and the host microcontroller communicate using a single wire, bi-directional asynchronous serial interface. the bit rate is automatically determined by the SH3003. at the fastest possible rate, a read or write access of a single byte from the register bank takes 5 s. the SH3003 contains thirty-six addressable registers located at 0x00?0x1f. some of these registers are ac- cessed through a page operation. pin 14, io/int, is the serial communications interface and interrupt output pin. this pin is internally weakly pulled to the opposite of the programmed interrupt polarity. for example, if interrupt is programmed to be active low, this pin is weakly pulled to v dd when inactive. as shown in figure 7, the SH3003 and the host commu- nicate with serial data streams. the host always initiates communication. a data stream consists of the following (in this order): ? 3-bit start eld ? 3-bit read/write code ? 5-bit address eld ? 1 guard bit ? 8-bit data eld ? 2 parity bits plus, for write streams only: ? 1 guard bit ? 2 acknowledge (ack) bits the 3-bit start eld (1,0,1 or 0,1,0, depending on interrupt polarity) uses the middle bit to determine the bit period of the serial data stream. the 3-bit read/write code consists of 1,1,0 for a read, or 0,1,1 for a write. this protects against early glitches that might otherwise put the interface into an invalid read or write access mode. the 5-bit address eld contains the address of the regis- ter. a single guard bit gives the interface a safe period in which to change data direction. the value of a guard bit does not matter. the 8-bit data eld is written to (read from) the register. two parity bits: the rst parity bit is high when there are an odd number of bits in the read/write, address and data elds; the second parity bit is the inverse of the rst. for write streams only, a guard bit is appended to the stream (to allow safe turnaround), and then two acknowl- edge bits, which are a direct copy of the parity bits, are driven back to the host to indicate a successful write ac- cess. two guard bits are appended to the end of the access stream (read or write). the host can not start the next ac- cess before receiving these bits. the interface is self-timed based on the duration of the start bit eld, and communication can take place when- ever clkout is active, either at 32.768khz or at a higher frequency. if the host microcontroller is running synchro- nously to the clkout generated by the SH3003 (which should generally be the case), then a minimum of four clkout cycles per bit are required to maintain communi- cation integrity. if the host?s serial interface is asynchro- nous to clkout, then a minimum of 52 cycles per bit are necessary. a maximum of 1024 clkout cycles per bit eld is supported. table 3 displays the minimum and maximum bit periods for the serial communications for clkout frequencies of 16 mhz, 8mhz, and 2mhz. interrupt and serial interface
? 2006 semtech corp. www.semtech.com power management 21 SH3003 power management interrupt and serial interface (continued) application information (continued) interrupt interface the serial communications line to the SH3003 (pin 14, io/int) also serves as the interrupt to the host microcontroller. the polarity of the interrupt is software programmable using the interrupt polarity bit (bit 6) of the ipol_rctune register (r0x11). this pin is asserted for four cycles of clkout, and then returns to the inactive state. the interrupt line is used by the periodic interrupt/wake-up timer to interrupt the host when it reaches its end of count. clk out frequency minimum bit period (host synchronous to clk out ) minimum bit period (host asynchronous to clk out ) maximum bit period 16mhz 250ns 3.25 s 63.9 s 8mhz 500ns 6.5 s 127 s 2mhz 2 s26 s511 s table 3 - minimum/maximum serial bit timing
22 ? 2006 semtech corp. SH3003 www.semtech.com not authorized for release outside of semtech - draft power management application information (continued) 1. int disabled, up initiates write access. active high interrupt. ubuddyioout upioout a0 a4 xxx d0 d7 ... combinedio a0 a4 xxx d0 d7 ... ... 2. int active (high), up initiates write access ubuddyioout upioout combinedio xxx state idle pre- start start post- start a0 a4 guard0 d0 d7 ... ... guard1 idle xxx state if the interrupt did not get cleared, then it will activate again here 4. int disabled, up initiates read access ubuddyioout upioout a0 a4 xxx ... combinedio a0 a4 xxx d0 d7 ... ... state idle pre- start start post- start a0 a4 guard0 d0 d7 ... ... guard2 idle d0 d7 ... p0 p1 p0 p1 p0 p1 p0 p1 p0 p1 p0 p1 ack0 ack1 ack0 ack1 ack0 ack1 rw0 rw1 rw2 a0 a4 xxx d0 d7 ... a0 a4 xxx d0 d7 ... ... xxx pre- start start post- start a0 a4 guard0 d0 d7 ... ... guard1 xxx p0 p1 p0 p1 p0 p1 ack0 ack1 ack0 ack1 rw0 rw1 rw2 ack0 ack1 guard2 guard3 guard2 guard3 pendin g-start in t idle pendin g-start in t 3. int active (low), up initiates write access ubuddyioout upioout combinedio state if the interrupt did not get cleared, then it will activate again here a0 a4 xxx d0 d7 ... a0 a4 xxx d0 d7 ... ... xxx pre- start start post- start a0 a4 guard0 d0 d7 ... ... guard1 xxx p0 p1 p0 p1 p0 p1 ack0 ack1 ack0 ack1 rw0 rw1 rw2 guard2 guard3 pendin g-start in t idle pendin g-start in t ack0 ack1 rw0 rw1 rw2 guard3 io/int timing scenarios figure 7. serial communication timing diagram
? 2006 semtech corp. www.semtech.com power management 23 SH3003 power management typical characteristics free running hf dco frequency deviation over temperature for all frequencies -16000 -14000 -12000 -10000 -8000 -6000 -4000 -2000 0 2000 4000 -60 -40 -20 0 20 40 60 80 100 120 140 temp. oc ppm deviation internal 32.768 khz oscillator frequency over temperature 31800 32000 32200 32400 32600 32800 33000 33200 33400 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (oc) frequency (hz)
24 ? 2006 semtech corp. SH3003 www.semtech.com not authorized for release outside of semtech - draft power management typical characteristics (continued) 32.768 khz crystal oscillator frequency deviation over temperature -200 -150 -100 -50 0 50 -60 -40 -20 0 20 40 60 80 100 120 temperature (oc) ppm deviation battery backup current over temperature (v bak = 3 v) 0 2 4 6 8 10 12 14 16 18 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (oc) v bak current (a) internal 32.768 khz crystal 32.768 khz
? 2006 semtech corp. www.semtech.com power management 25 SH3003 power management typical characteristics (continued) standby current over temperature (v dd = 5 v) 0.0 5.0 10.0 15.0 20.0 25.0 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (oc) v dd current (a) crystal 32.768 khz internal 32.768 khz standby current over v dd (temp. = 25oc) 4 5 6 7 8 9 10 2.5 3 3.5 4 4.5 5 5.5 v dd (v) v dd current (a) crystal 32.768 khz internal 32.768 khz
26 ? 2006 semtech corp. SH3003 www.semtech.com not authorized for release outside of semtech - draft power management typical characteristics (continued) v dd current vs clkout frequency (v dd = 5.5 v, temp. = 25oc) 0 500 1000 1500 2000 2500 3000 3500 0 2 4 6 8 1012141618 frequency (mhz) v dd current (a) operating v dd current over v dd (clkout = 16 mhz, temp = 25oc) 2000 2200 2400 2600 2800 3000 3200 2.5 3 3.5 4 4.5 5 5.5 v dd (v) v dd current (a)
? 2006 semtech corp. www.semtech.com power management 27 SH3003 power management typical characteristics (continued) free running hf dco short term frequency stability (clkout = 8 mhz) -400 -300 -200 -100 0 100 200 300 -500 500 1500 2500 3500 4500 5500 6500 time (seconds) ppm deviation fll locked hf dco jitter over jitter bandwidth (clkout = 12.8 mhz) 10 100 1000 10000 100000 0.1 1 10 100 1000 10000 100000 jitter bandwidth (khz) rms jitter (ps)
28 ? 2006 semtech corp. SH3003 www.semtech.com not authorized for release outside of semtech - draft power management outline drawing - mlp 3 x 3 mm 16 pins
? 2006 semtech corp. www.semtech.com power management 29 SH3003 power management land pattern - mlp 3 x 3 mm 16 pins
30 ? 2006 semtech corp. SH3003 www.semtech.com not authorized for release outside of semtech - draft power management semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 contact information www.semtech.com copyright ?2002-2006 semtech corporation. all rights reserved. semtech, the semtech logo, microbuddy, buddy, and b are marks of semtech corporation. all other marks belong to their respective owners. changes may be made to this product without notice. customers are advised to obtain the latest version of the relevant informa - tion before placing orders. limited license granted: no warranties made this speci cation is provided ?as is? with no warranties whatsoever including any warranty of merchantability, tness for any par- ticular purpose, or any warranty otherwise arising out of any proposal, speci cation or sample. any suggestions or comments by semtech concerning use of this product are opinion only, and semtech makes no warranty as to results to be obtained in any spe- ci c application. a license is hereby granted to reproduce and distribute this speci cation for internal use only. no other license, expressed or implied to any other intellectual property rights is granted or intended hereby. authors of this speci cation disclaim any liability, including liability for infringement of proprietary rights, relating to the implementation of information in thi s speci ca- tion. authors of this speci cation also do not warrant or represent that such implementation(s) will not infringe such rights.

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